Guest
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 Posted:
Fri Aug 12, 2005 8:20 am Post subject:
Interpreting Intel 82450EM Ethernet Controller Stats |
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Hello,
I'm running a system based on Linux 2.4.31 with three Intel 82450EM
gigabit Ethernet ports. In trying to diagnose a througput problem, I'm
using ethtool to look at the controller registers, but I'm not sure how
to interpret the values of RDH and RDT (receive descriptor head/tail).
Given output like:
[TEST] root # ethtool -d eth2
MAC Registers
-------------
0x00000: CTRL (Device control register) 0x083C0249
Duplex: full
Endian mode (buffers): little
Link reset: reset
Set link up: 1
Invert Loss-Of-Signal: no
Receive flow control: enabled
Transmit flow control: disabled
VLAN mode: disabled
Auto speed detect: disabled
Speed select: 1000Mb/s
Force speed: no
Force duplex: no
0x00008: STATUS (Device status register) 0x0000C383
Duplex: full
Link up: link config
TBI mode: disabled
Link speed: 1000Mb/s
Bus type: PCI
Bus speed: 33MHz
Bus width: 32-bit
0x00100: RCTL (Receive control register) 0x0000801A
Receiver: enabled
Store bad packets: disabled
Unicast promiscuous: enabled
Multicast promiscuous: enabled
Long packet: disabled
Descriptor minimum threshold size: 1/2
Broadcast accept mode: accept
VLAN filter: disabled
Cononical form indicator: disabled
Discard pause frames: filtered
Pass MAC control frames: don't pass
Receive buffer size: 2048
0x02808: RDLEN (Receive desc length) 0x00010000
0x02810: RDH (Receive desc head) 0x000008D8
0x02818: RDT (Receive desc tail) 0x000008D0
0x02820: RDTR (Receive delay timer) 0x00000000
0x00400: TCTL (Transmit ctrl register) 0x000400FA
Transmitter: enabled
Pad short packets: enabled
Software XOFF Transmission: disabled
Re-transmit on late collision: disabled
0x03808: TDLEN (Transmit desc length) 0x00001000
0x03810: TDH (Transmit desc head) 0x00000036
0x03818: TDT (Transmit desc tail) 0x00000036
0x03820: TIDV (Transmit delay timer) 0x00000040
PHY type: M88
where RDH is 000008D8 and RDT is 000008D0, does this mean that the
descriptor ring buffer has 8 free descriptors, or 8 used descriptors?
It's curious that RDH always seems to be numerically higher than RDT.
In practice, I've never seen the situation reversed.
Oh, and a second question. As you can see, the "ethtool -d" output
doesn't show anywhere close to the full register dump. Is there a tool
I can use to access registers not shown here, or do I need to start
hacking ethtool?
Thanks!
G |
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Capt. James. T. Kirk
Guest
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| Posted:
Mon Aug 29, 2005 7:27 am Post subject:
Re: Interpreting Intel 82450EM Ethernet Controller Stats |
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gg-csf@dmztest.vsr.ambisys.net wrote:
| Quote: | Hello,
I'm running a system based on Linux 2.4.31 with three Intel 82450EM
gigabit Ethernet ports. In trying to diagnose a througput problem, I'm
using ethtool to look at the controller registers, but I'm not sure how
to interpret the values of RDH and RDT (receive descriptor head/tail).
Given output like:
|
Ouch... I can tell you right away, you WILL have throughput problem of
cramming 3 GIGAbit Ethernet on one pitiful 33Mhz PCI bus... Your PCI
backplane is choking at 600Mbps total to be shared across 3 gigabit
ethernet card (and that is with a 2.1 Ghz CPU).
Go invest in a mother board with PCI 66Mhz or 100Mhz bus, preferably
with 64-bit wide PCI connectors.
ALso invest in Intel 1000 ST cards. These are server cards with wide
PCI bus.
Then repeat your throughput test.
| Quote: |
[TEST] root # ethtool -d eth2
MAC Registers
-------------
0x00000: CTRL (Device control register) 0x083C0249
Duplex: full
Endian mode (buffers): little
Link reset: reset
Set link up: 1
Invert Loss-Of-Signal: no
Receive flow control: enabled
Transmit flow control: disabled
VLAN mode: disabled
Auto speed detect: disabled
Speed select: 1000Mb/s
Force speed: no
Force duplex: no
0x00008: STATUS (Device status register) 0x0000C383
Duplex: full
Link up: link config
TBI mode: disabled
Link speed: 1000Mb/s
Bus type: PCI
Bus speed: 33MHz
Bus width: 32-bit
0x00100: RCTL (Receive control register) 0x0000801A
Receiver: enabled
Store bad packets: disabled
Unicast promiscuous: enabled
Multicast promiscuous: enabled
Long packet: disabled
Descriptor minimum threshold size: 1/2
Broadcast accept mode: accept
VLAN filter: disabled
Cononical form indicator: disabled
Discard pause frames: filtered
Pass MAC control frames: don't pass
Receive buffer size: 2048
0x02808: RDLEN (Receive desc length) 0x00010000
0x02810: RDH (Receive desc head) 0x000008D8
0x02818: RDT (Receive desc tail) 0x000008D0
0x02820: RDTR (Receive delay timer) 0x00000000
0x00400: TCTL (Transmit ctrl register) 0x000400FA
Transmitter: enabled
Pad short packets: enabled
Software XOFF Transmission: disabled
Re-transmit on late collision: disabled
0x03808: TDLEN (Transmit desc length) 0x00001000
0x03810: TDH (Transmit desc head) 0x00000036
0x03818: TDT (Transmit desc tail) 0x00000036
0x03820: TIDV (Transmit delay timer) 0x00000040
PHY type: M88
where RDH is 000008D8 and RDT is 000008D0, does this mean that the
descriptor ring buffer has 8 free descriptors, or 8 used descriptors?
It's curious that RDH always seems to be numerically higher than RDT.
In practice, I've never seen the situation reversed.
|
One in 8 times, you will see the RDH fall behind to RDT during ring
buffer wraparound....
| Quote: |
Oh, and a second question. As you can see, the "ethtool -d" output
doesn't show anywhere close to the full register dump. Is there a tool
I can use to access registers not shown here, or do I need to start
hacking ethtool?
|
Hack your own... |
|
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